MEMS Engineering and Material Processing

Get Quote

Terms and Conditions
Lead time 6-8 weeks, built to order 


  • SOI wafer  with uniformity of +/-0.5  µ by grinding and polishing;
  • Ultra uniform SOI  wafer with uniformity of +/-0.15 µ by layer transfer;
  • New engineering substrate (such as GaAs/Si, glass/Glass)
  • Resist coating, contact & step expose, develop. Lift off process.

With our partners in Asia we provide the following wafer foundry services to semiconductor and MEMS industry from single process to  proto-type product to high volume capacity.

  • SOI wafer  with uniformity of +/-0.5  µ by grinding and polishing;
  • Ultra uniform SOI  wafer with uniformity of +/-0.15 µ by layer transfer;
  • New engineering substrate (such as GaAs/Si, glass/Glass)

Ultra uniform SOI  by layer transfer Currently thick SOI wafer ( > 2.0 µ device thickness) by most manufacturers is made through  grinding and polishing process. Due to inherent properties of grinding and polishing, the best thickness uniformity by this process is +/-0.5 µ. This is large thickness variation for thickness below 5 µ SOI wafers. For typical 2.0 µ SOI wafer, this represents +/-25% thickness variation. In  MEMS sensors, such as pressure sensor, sensitivity of  the sensor is directly related to SOI membrane thickness. So large variation of thickness will cause poor device  properties. We are making this ultra uniform SOI wafers through layer transfer instead of grinding and polishing.  The thickness uniformity through our proprietary layer transfer can be as uniform as +/-0.15µ. We also provide SOI wafers with uniformity of +/0.5 µ through grinding and polishing. Our SOI wafers are widely used in the following areas: 1. MEMS; 2. Smart sensors; 3. Power devices 4.Semiconductor. Advantage of MEMS Engineering & Material ; 1. Flexibility, thickness of wafer and oxide, resistivity of wafer; 2. Skilled staff in MEMS, work with you to design SOI for robust MEMS process; Silicon On Glass Silicon on glass wafers are fabricated by anodic bonding which relies on charge migration to create bonded wafers. By applying certain negative potential to the glass at elevated temperature, sodium ions in the glass are driven to negative electrode to create a space charge at the glass-silicon interface. This space charge gives a strong electrostatic forces between the silicon and glass that holds both pieces. Oxygen from glass simultaneously transfers to the interface of glass and silicon to form silicon oxide, which creates a permanent bonding. Our silicon on glass wafer can be used in the following applications: 1. Pressure sensors; 2. Solar cell; 3. Packaging; 4. Optical components. Other Bonded Structures; MEMS Engineering & Material  has the capability to fabricate other bonded structures, such as Glass to glass, SOS (silicon on Sapphire), GaAs/Si,  InP/Si for the application of MEMS and semiconductor industry. We also like to establish partnership with our customers to develop customized bonded structures bashing on our bonding technologies. Other process offer: 1. Thin Film Coating

  • Metal(Au,Cr,Al,Cu,Ni,Pt) thin film, SiO2, SiN by sputtering, evaporation, and CVD.

2. Photolithography Process

  • Resist coating, contact & step expose, develop. Lift off process.

3. Electroplating and Electroless Plating

  • Cu, Ni, Au, Solder for interconnect and wafer  bumping.

4. Etching

  • Wet and dry etching.

5. Wafer Bonding

  • Fusion, anodic, eutectic, polyimide, polymer bonding.

6. Dicing

  • Silicon, glass.

7. Grinding and Polishing

  • Silicon wafer grinding and CMP polishing.

We provide low stress SOI wafers with flexibility in device wafers, buried oxide, and  handle wafers. We also provide  silicon on glass  and other  bonded structures. Contact us for more information. The following is the specification for our standard SOI  wafers;    

3" 4" 5" 6"
Device waferTypeResistivity Orientation Thickness Tolerance P, N0.01~100W.cm <100>,<110> 2~200 µ +/- 0.5 µ P, N0.01~100W.cm <100>,<110> 2~200 µ +/- 0.5 µ P, N0.01~100W.cm <100>,<110> 2~200 µ +/- 0.5 µ P, N0.01~100W.cm <100>,<110> 2~200 µ +/- 1.0 µ
BOXThicknessUniformity 0.5~3.0µ+/-5% 0.5~3.0µ+/-5% 0.5~3.0µ+/-5% 0.5~3.0µ+/-5%
Handle waferTypeResistivity Orientation Thickness Tolerance P, N0.01~100W.cm <100>,<110> 250~400 µ +/- 2 µ P, N0.01~100W.cm <100>,<110> 300~625 µ +/- 2 µ P, N0.01~100W.cm <100>,<110> 350~625 µ +/-2 µ P, N0.01~100W.cm <100>,<110> 400~625 µ +/- 3 µ